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-- Modelo diagonales --
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity diagonals is port

(xpix, ypix: in std_logic_vector(9 downto 0);
r, g, b: out std_logic);

end;

architecture bhr of diagonals is
signal num: std_logic_vector(9 downto 0);
begin

num <= xpix + ypix;
r <= num(9);
g <= num(8);
b <= num(7);

end;