---------------------------------------------
-- PWM --
---------------------------------------------
-- Programa modulador en amplitud de pulso
-- Periodo: P = 1 hasta 2**n-1 ==> P+1 ciclos (P=0 no hace nada)
-- Pulso: W=1 hasta 2**n-1 ==> pulso de W ciclos de P (W=0 no hace nada)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pwm2 is

generic(n: integer := 32); --num bits pwm
port

(ck, nReset, enable: in std_logic;
periode, pols: in std_logic_vector(n-1 downto 0);
pw: out std_logic);

end;
architecture rtl of pwm2 is
signal count: integer range 0 to 2**n-1;
begin

periodePWM: process (nReset, ck)
begin

if (nReset='0') then count <= 0;
elsif ck'event and ck='1' then

if enable = '1' then

if count < periode then count <= count+1;
else count <= 0;
end if;

else count <= count;
end if;

end if;

end process;
salida:
process
begin

wait until ck='0';
if (count<conv_integer(pols)) then pw <= '1';
else pw <= '0';
end if;

end process;

end;


WcN - Joan Oliver. Diseño de circuitos digitales con VHDL