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-- Modelo test de controlador de VGA --
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library ieee;
use ieee.std_logic_1164.all;

entity VGA_testSimple is end;

architecture test of VGA_testSimple is
component VGA

port(

clock, r, g, b: in std_logic; -- Reloj, rojo, verde, azul (entradas)
r_out, g_out, b_out: out std_logic; -- Rojo, verde, azul (salidas)
h_sinc, v_sinc: out std_logic; -- Sincronismo vertical y horizontal (salidas)
pixel_r, pixel_c: out std_logic_vector(9 downto 0));

end component;

signal clock : std_logic:='0';
signal r, g, b: std_logic:='1';
signal r_out, g_out, b_out, h_sinc, v_sinc: std_logic;
signal pixel_r, pixel_c: std_logic_vector(9 downto 0):="0000000000";

begin

comp: VGA port map (clock, r, g, b, r_out, g_out, b_out, h_sinc, v_sinc, pixel_r, pixel_c);
clock <= not(clock) after 1 ns;

end;