---------------------------------------------
-- Wrapper --
---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity registresPWM is

generic(n:integer:=32); --Ancho bus avalon
port

(ck, nReset, chipselect, write, read: in std_logic;
address: in std_logic_vector(1 downto 0); -- bus Avalon
writeData: in std_logic_vector(n-1 downto 0);
readData: out std_logic_vector(n-1 downto 0);
enable: out std_logic; --Senyals mòdul pwm
periode, pols: out std_logic_vector(n-1 downto 0));

end;
architecture rtl of registresPWM is
signal lectura, escriptura, selPer, selPols, selEnbl, enLectPer: std_logic;
signal enLectPols, enLectEnbl, enRegPer, enRegPols, enRegEnbl: std_logic;
signal regPer, regPols: std_logic_vector(n-1 downto 0); --Modulo pwm
signal regEnbl: std_logic;
begin

lectura <= chipselect and read;
escriptura <= chipselect and write;
selPer <= not(address(1)) and not(address(0)); --Seleccion periodo
selPols <= not(address(1)) and address(0); --Seleccion ancho
selEnbl <= address(1) and not(address(0)); enLectPer <= lectura and selPer; --Habilitación PWM
enLectPols <= lectura and selPols;
enLectEnbl <= lectura and selEnbl;
enRegPer <= escriptura and selPer;
enRegPols <= escriptura and selPols;
enRegEnbl <= escriptura and selEnbl;
lecturaBus: process(enLectPer, enLectPols, enLectEnbl, chipselect, read)
begin

if enLectPer='1' then readData <= regPer;
elsif enLectPols='1' then readData <= regPols;
elsif enLectEnbl='1' then

readData(n-1 downto 1) <= (others => '0');
readData(0) <= regEnbl;
else readData <= (others => '0');

end if;

end process;
loadRegPer: process (nReset, ck)
begin

if nReset='0' then regPer <= (others => '0');
elsif ck'event and ck='1' then

if enRegPer = '1' then regPer <= writeData;
else regPer <= regPer;
end if;

end if;

end process;
loadRegPols: process (nReset, ck)
begin

if nReset='0' then regPols <= (others => '0');
elsif ck'event and ck='1' then

if enRegPols = '1' then regPols <= writeData;
else regPols <= regPols;
end if;

end if;

end process;
loadRegEnbl: process (nReset, ck)
begin

if nReset='0' then regEnbl <= '0';
elsif ck'event and ck='1' then

if enRegEnbl = '1' then regEnbl <= writeData(0);
else regEnbl <= regEnbl;
end if;

end if;

end process;
periode <= regPer; --Salidas
pols <= regPols;
enable <= regEnbl;

end;