-- Retardos
--------------------------------------------------------------------------
---- Para el uso de Reject activar la opción VHDL'93 del compilador
--------------------------------------------------------------------------

-- Declaración de la entidad
Entity onda is
end onda ;

-- Definición de la arquitectura
Architecture forma of onda is
Signal o, s1, s2, s3, s4: bit;
begin

o <= '0', '1' after 3 ns, '0' after 8 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns,
'0' after 27 ns, '1' after 33 ns, '0' after 39 ns, '1' after 44 ns, '0' after 48 ns;

s1 <= transport o after 5 ns;
s2 <= o after 5 ns; --inertial o after 5 ns;
s3 <= reject 3 ns inertial o after 5 ns;
s4 <= transport o after 5 ns;

end forma;


WcN - Joan Oliver. Diseño de circuitos digitales con VHDL