-- Modelo de verificación usando el package
-- Se debe utilizar la librería work que es donde está definico el package
Library work;
Use work.vectorsx.ALL;
Entity autotestXTaula2 is

port (okq: out bit);

end;
Architecture bhr of autotestXTaula2 is
Component compt_x

port(ck, enable, load: in bit;
d: in natural range 0 to 15;
q: out natural range 0 to 15);

end component;
signal ck, enable, load: bit;
signal d, q, testq: natural range 0 to 15;
begin

compt: compt_x port map (ck, enable, load, d, q);
ck <= not ck after 2 ns;
process
variable i: integer range 0 to test'high;
begin

enable <= test(i).enable;
load <= test(i).load;
d <= test(i).d;
wait until ck'event and ck='1'; --Aplicación vector de verificación
testq <= test(i).q;
i := i+1;
wait for 1 ns; -- Retardo delta

end process;
okq <= '0' when testq=q else '1';

end bhr;