-- Latx SR
-- Se documenta la incidencia 'salidas iguales'

entity SR is

port (S, R: in bit;
Q, nQ: inout bit);

end;
architecture bhr of SR is
signal delta: time := 1 ns;
begin

Q <= R nor nQ after delta; -- Funcionamiento latch
nQ <= S nor Q after delta;
assert now=0 fs or Q=not nQ -- Se documenta la incidencia

report "Inconsistència: Q=" & Q'image(Q) &
" nQ=" & nQ'image(nQ)
severity warning;

end;