--Descripción del fichero de test de SR
entity SRtest is
end;
architecture test of SRtest is
component SR
port (

S, R: in bit;
Q, nQ: inout bit);

end component;
signal S, Q: bit:='1';
signal R, nQ: bit:='0';
begin

ff: SR port map (S, R, Q, nQ);
process
variable t: time := 5 ns;
begin

R <= not R after 2*t;
S <= not S after 4*t;
wait for 1 ns; -- Provar otros tiempos de espera...

end process;

end;