-- Contador up/down

Library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.ALL;

--Definición de la entidad
entity cont is

generic(n: integer := 3);
port(

Reset, ck, enable, UnD: in std_logic;
q: out std_logic_vector(n-1 downto 0);
tc: out std_logic);

end;

--Arquitectura
architecture rtl of cont is
signal t:time:=0.5 ns; -- Simulación de retardo en las salidas
signal c: integer range 0 to 2**n-1;
begin

process
begin

wait until ck='1';
if nReset='0' then c<=0; -- Reset síncrono
elsif enable='1' then -- Capacitación de conteo

if UnD='1' then -- Cuenta up

if c=2**n-1 then c <= 0; --Comprobación de fin de cuenta
else c <= (c+1);
end if;

else -- Cuenta down

if c=0 then c <= 2**n-1; --Comprobación de fin de cuenta
else c <= (c-1);
end if;

end if;

end if;

end process;
q <= conv_std_logic_vector(c,n) after t; -- Salida estado
tc <= '1' after t when c=(2**n-1) else '0' after t; -- Salida terminal counter

end;