-- Multiplexor
--Especificación RTL: una entidad, tres arquitecturas
--Especificación de librerías
Library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
--Definición de la entidad
Entity mux_rtl is port

(x: in std_logic_vector(7 downto 0);
s: in std_logic_vector(2 downto 0);
z: out std_logic);

end mux_rtl;
--Arquitectura 1: uso de asignación concurrente mediante when...else
Architecture rtl_1 of mux_rtl is
begin

z<= x(0) when s="000" else
x(1) when s="001" else
x(2) when s="010" else
x(3) when s="011" else
x(4) when s=4 else
x(5) when s=5 else
x(6) when s=6 else
x(7);

end rtl_1;
--Arquitectura 2: uso de asignación concurrente mediante with...select
Architecture rtl_2 of mux_rtl is
begin

with s select

z<= x(0) when "000",
x(1) when "001",
x(2) when "010",
x(3) when "011",
x(4) when "100",
x(5) when "101",
x(6) when "110",
x(7) when others;

end rtl_2;
--Arquitectura 3: uso de case en un process
Architecture rtl_3 of mux_rtl is
begin

process(x, s)

begin

case s is

when "000" => z<=x(0);
when "001" => z<=x(1);
when "010" => z<=x(2);
when "011" => z<=x(3);
when "100" => z<=x(4);
when "101" => z<=x(5);
when "110" => z<=x(6);
when "111" => z<=x(7);

end case;

end process;

end rtl_3;