-- Contador up/down

Library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.ALL;

--Definición de la entidad
entity sr is

generic(n: integer := 3);
port(

ck, ir, il: in std_logic;
ctrl: in std_logic_vector(1 downto 0);
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0));

end;

--Arquitectura
architecture rtl of sr is
signal t:time:=0.5 ns; -- Simulación de retardo en las salidas
signal c: std_logic_vector(N-1 downto 0);
begin

process
begin

wait until ck='1';
case conv_integer(ctrl) is

when 0 => c(N-1 downto 0) <= d; -- Carga paralela
when 1 => c(N-1 downto 0) <= c(N-2 downto 0) & ir; --Desplazamiento a izquierda
when 2 => c(N-1 downto 0) <= il & c(N-1 downto 1) ; -- Desplazamiento a derecha
when others => c <= c; -- Mantener estado

end case;

end process;
q <= c;

end;