-- Sumador/Restador
--Especificación comportamental

Library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;

Entity SumaDif is

generic (n:integer:=4);
port (

a, b:in std_logic_vector(n-1 downto 0);
cin, sel:in std_logic;
s_d:out std_logic_vector(n-1 downto 0);
co: out std_logic);

end SumaDif;
Architecture bhr of SumaDif is
signal s: std_logic_vector (n downto 0);
begin

process (a, b, cin, sel)
begin

if sel='0' then s <= ('0' & a) + b +cin;
else s <= ('0' & a) - (b + cin);
end if;

end process;
s_d <= s(n-1 downto 0);
co <= s(n);

end;