-- Bus tri-state
--Especificación comportamental

Library ieee;
use ieee.std_logic_1164.ALL;

--Definición de la entidad
Entity tris is port

(a, b: in std_logic_vector(1 downto 0);
ae, be: in std_logic;
y: inout std_logic_vector(1 downto 0));

end tris;

--Arquitectura
Architecture func of tris is
begin

process (a, ae)
begin

if (ae='1') then y <= a;
else y <= (others => 'Z');
end if;

end process;
process(b, be)
begin

if (be='1') then y <= b;
else y <= (others => 'Z');
end if;

end process;

end func;


WcN - Joan Oliver. Diseño de circuitos digitales con VHDL